1. Field of the Invention
The invention relates to a reference buffer circuit, and more particularly to a reference buffer circuit for providing at least one reference voltage to an analog-to-digital converter, regulator or the like.
2. Description of the Related Art
Reference buffer circuits are required for high-speed and high-resolution analog-to-digital converters (ADCs). A reference buffer circuit usually comprises a reference buffer and provides at least one reference voltage to an ADC. There are two types of reference buffer circuits available for ADCs: closed-loop reference buffer circuits and open-loop reference buffer circuits.
FIG. 1 shows a conventional closed-loop reference buffer circuit 1. An amplifier 10 has a negative feedback loop. The amplifier 10 receives an input voltage Vref_in at a positive input terminal and outputs a reference voltage Vref. The output impedance of the reference buffer circuit 1 is equal to ROUT/(1+A), wherein ROUT represents the output impedance of the amplifier 10, and A represents the gain thereof. When the reference buffer circuit 1 operates at a high frequency, the output impedance of the reference buffer circuit 1 is required to be low enough to rapidly stabilize the reference voltage Vref. However, the wide bandwidth causes the power consumption and noise of the reference buffer circuit 1 to be increased. It is difficult to design an internal closed-loop reference buffer circuit for a high-resolution ADC.
FIG. 2 shows a conventional single-ended open-loop reference buffer circuit. A single-ended open-loop reference buffer circuit 2 comprises an amplifier 20, N-type metal oxide semiconductor (NMOS) transistors 21 and 22, and load units 23 and 24. The operation of the NMOS transistor 22 is similar to the NMOS transistor 21. The amplifier 20 and the NMOS transistor 21 form a negative feedback loop, while the NMOS transistor 22 is disposed in an open-loop circuit. In steady state, reference voltage Vref tracks reference voltage Vrefx. Moreover, the output impedance of the open-loop reference buffer circuit 2 is equal to 1/gm, wherein gm represents the transconductance of the NMOS transistor 22, and the bandwidth of the amplifier 20 can be narrower, the power consumption of the open-loop reference buffer circuit 2 is less than that of the closed-loop reference buffer circuit 1 as illustrated in FIG. 1.
FIG. 3 shows a conventional differential open-loop reference buffer circuit. A differential open-loop reference buffer circuit 3 comprises amplifiers 30 and 31, NMOS transistors 32 and 33, P-type metal oxide semiconductor (PMOS) transistors 34 and 35, and resistors 36 and 37. Positive input terminals of the amplifiers 30 and 31 respectively receive input voltages Vrefp_in and Vrefn_in. The amplifier 30 and the NMOS transistor 32 form one negative feedback loop, and the amplifier 31 and the PMOS transistor 34 form the other negative feedback loop. The NMOS transistor 33 is disposed in one open-loop circuit, and the PMOS transistor 35 is disposed in the other open-loop circuit. In steady state, reference voltages Vrefp and Vrefn respectively track reference voltages Vrefpx and Vrefnx.
In FIG. 2, there is a voltage difference between the gate and the source of each of the NMOS transistors 21 and 22 which are both operated in saturation region, and the voltage of an output terminal of the amplifier 20 is larger than the reference voltage Vrefx by the voltage difference, so that a required supply voltage of the open-loop reference buffer circuit 2 is large. If the open-loop reference buffer circuit 2 operates under a low supply voltage due to design requirements, the maximum value of the reference voltage Vref is suppressed to be small. Similarly, in FIG. 3, there is a voltage difference between the gate and the source of each of the NMOS transistors 32 and 33 and there is a voltage difference between the gate and the source of each of the PMOS transistors 34 and 35, and the maximum value of the reference voltage Vrefp and the minimum values of the reference voltage Vrefn are limited when the open-loop reference buffer circuit 3 operates under a low supply voltage, so that the swing between the reference voltages Vrefp and Vrefn is hard to meet design requirements.
With the advancement of semiconductor processes, the operation voltage of semiconductor decreases. Thus, a reference buffer circuit, which can operate under low supply voltage, can provide reference voltages with large swing, and has less power consumption and high operation speed, is required.